IMSAI 8080 bus

From HwB

Used in IMSAI 8080.

Contents

Pinout

1     (Component side)      50
==============================
100     (Solder side)       51
Pin Name Type Dir Description
1 +8 V Power Arrowr.png +8 Volts
2 +18 V Power Arrowr.png +18 Volts
3 XRDY Fr panel Arrowr.png External Ready To Processor
4 VI 0 Control Arrowl.png Vector Interrupt Line 0
5 VI 1 Control Arrowl.png Vector Interrupt Line 1
6 VI 2 Control Arrowl.png Vector Interrupt Line 2
7 VI 3 Control Arrowl.png Vector Interrupt Line 3
8 VI 4 Control Arrowl.png Vector Interrupt Line 4
9 VI 5 Control Arrowl.png Vector Interrupt Line 5
10 VI 6 Control Arrowl.png Vector Interrupt Line 6
11 VI 7 Control Arrowl.png Vector Interrupt Line 7
12
13
14
15
16
17
18 /STADSB Control Arrowl.png Disable Processor Status Lines
19 /CCDSB Control Arrowl.png Disable Processor Control Lines
20 T5  ?  ? T5?
21 SS Fr panel Arrowr.png Single Step Processor
22 /ADDDSB Control Arrowl.png Disable Processor Address Lines
23 /DODSB Control Arrowl.png Disable Processor Data Out Lines
24 phi2 Clock Arrowr.png Primary Processor Clock Line
25 phi1 Clock Arrowr.png "Inversion" Of Phase 2 Processor Clock Line
26 PHLDA Control Arrowr.png Processor In Hold Condition
27 PWAIT Control Arrowr.png Processor In Wait Condition
28 PINTE Control Arrowr.png Processor Permits Interrupts When Active
29 A5 Address Arrowr.png Address Line 5
30 A4 Address Arrowr.png Address Line 4
31 A3 Address Arrowr.png Address Line 3
32 A15 Address Arrowr.png Address Line 15
33 A12 Address Arrowr.png Address Line 12
34 A9 Address Arrowr.png Address Line 9
35 DO1 Data Arrowr.png Data Output Line 1
36 DO0 Data Arrowr.png Data Output Line 0
37 A10 Address Arrowr.png Address Line 10
38 DO4 Data Arrowr.png Data Output Line 4
39 DO5 Data Arrowr.png Data Output Line 5
40 DO6 Data Arrowr.png Data Output Line 6
41 DI2 Data Arrowl.png Data Input Line 2
42 DI3 Data Arrowl.png Data Input Line 3
43 DI7 Data Arrowl.png Data Input Line 7
44 SM1 State Arrowr.png Processor Instruction Fetch Signal
45 SOUT State Arrowr.png Processor I/O Write Signal
46 SINP State Arrowr.png Processor I/O Read Signal
47 SMEMR State Arrowr.png Processor Memory Read Signal
48 SHLTA State Arrowr.png Processor Halted Signal
49 /CLOCK Clock Arrowr.png 2Mhz Clock Signal
50 GND Power Arrow.png Logical And Power Ground
51 +8 V Power Arrowr.png +8 Volts
52 -18 V Power Arrowr.png -18 Volts
53 /SSW DSBL Fr panel Arrowr.png Sense Switch Disable (Of Data Inputs)
54 /EXTCLR Fr panel Arrowr.png Clear (Reset) I/O Devices On Bus
55
56
57
58
59
60
61
62
63
64
65
66
67 /PHANT  ?  ? Phantom?
68 MWRT Ctrl/frp Arrowr.png Memory Write From Processor Or Front Panel
69
70 GND Power Arrow.png Ground
71 RUN Fr panel Arrowr.png Stops Processor
72 PRDY Control Arrowl.png Controls Run/Wait State Of Processor
73 /PINT Control Arrowl.png Request For Interrupt To Processor
74 /PHOLD Control Arrowl.png Request For Hold To Processor
75 /PRESET Control Arrowl.png Forces Processor To Reset State
76 PSYNC Control Arrowr.png Marks Beginning Of Each Processor Cycle
77 /PWR Control Arrowr.png Active When Processor Writes (I/O Or Memory)
78 PDBIN Control Arrowr.png Active When Processor Reads (I/O Or Memory)
79 A0 Address Arrowr.png Address Line 0
80 A1 Address Arrowr.png Address Line 1
81 A2 Address Arrowr.png Address Line 2
82 A6 Address Arrowr.png Address Line 6
83 A7 Address Arrowr.png Address Line 7
84 A8 Address Arrowr.png Address Line 8
85 A13 Address Arrowr.png Address Line 13
86 A14 Address Arrowr.png Address Line 14
87 A11 Address Arrowr.png Address Line 11
88 DO2 Data Arrowr.png Data Output Line 2
89 DO3 Data Arrowr.png Data Output Line 3
90 DO7 Data Arrowr.png Data Output Line 7
91 DI4 Data Arrowl.png Data Input Line 4
92 DI5 Data Arrowl.png Data Input Line 5
93 DI6 Data Arrowl.png Data Input Line 6
94 DI1 Data Arrowl.png Data Input Line 1
95 DI0 Data Arrowl.png Data Input Line 0
96 SINTA Control Arrowr.png Acknowledge Signal For Pint Request
97 /SWO Control Arrowr.png Processor In Write Status
98 SSTACK Control Arrowr.png Processor In Stack Read/Write Status
99 /POC Ft panel Arrowr.png Power-On Clear Signal
100 GND Power Arrow.png Power And Signal Ground

Note: Direction is CPU/Frontpanel relative cards.

See also

Contributors

Sources